As the semiconductor technology continues to advance, electronic products are becoming thinner, lighter, shorter and smaller while the IC chips used in those electronic products are multifunction high I/O chips with high clock rate. Moreover, in the push to faster speed and lower power consumption, IC chips are continued to be scaled beyond the 90 nm node while materials of low-dielectric constant, i.e. low-K material, are used to fabricate internal wiring interconnects. The fabrication of low-k interconnects requires novel materials and processes, which give rise to technical bottlenecks in the packaging of integrated circuits, such as how to select a proper material for fabricating an IC, how to reduce stress and deformation resulting from thermal expansion mismatches between dissimilar materials during a packaging process, and so on.
As consumer continues to ask for, and purchase, smaller and smaller units, these demands eventually translate into more efficient designs in the packaging, such as BGA, Fine Pitch, Flip-Chip, CSP, etc., whereas, in general, small Pb—Sn solder bumps are built up directly on the pads of an IC chip while the IC chip is inverted and solder to pads on a circuit board. However, the aforesaid packaging technologies will cause the IC chip to subject to relative high thermal-induced stresses while inducing shear stresses to be generated between the IC chip and the circuit board. The stresses might cause the IC chip to be damaged or broken that not only will cause the device reliability to be reduced, but also have adverse effect on production yield. Furthermore, in order to integrate the low-K materials into advanced 90 nm interconnect processes, low-k materials need to meet a demanding list of electrical, mechanical, chemical and thermal integrity requirements to deliver the desired electrical performance, to enable compatibility with fabrication in module operation for high-volume manufacturing at high yield, and to ensure high device reliability in end use. However, the low-K material is generally poor to withstand thermal-induced stresses, so that it is important to have a manufacturing process of low stress.
The flip-chip bonding is the most commonly used and promising technique to meet the requirements for high-density packaging and high-frequency performance, which usually forms a layer of underfill encapsulating the solder bumps interconnecting a chip and a substrate for overcoming cracking caused by the thermal-induced stresses. In many cases, however, solder bumps are formed on the chip side, and then, many additional processes are needed in order to fabricate bumps on the integrated circuit (IC) chip. The additional processes lead to a decrease in chip production yield and an increase in production cost. Moreover, the Pb-based solder bump technique is problematic with respect to the environment. Recently, a variety of new flip-chip connecting methods have been developed. One of which is disclosed in U.S. Pat. No. 5,783,465, entitled “COMPLIANT BUMP TECHNOLOGY”, which describes an interconnection technique using compliant metal coated photodefined polymer bumps for mounting and interconnecting component assemblies on substrates such as glass, printed wiring boards, etc. The polymer chosen for the bump structure has relatively low Ts and the polymer bump is metallized in a way that substantially encapsulates the polymer, i.e. the polymer is wrapped in a conductive film. However, this so-called under-fill process requires time consuming steps of deposition and vacuum flow followed by curing. Second, if a chip is bad it cannot be removed once the under-fill has been applied and cured. Another such method is used in U.S. Pat. No. 6,818,544 and U.S. Pat. No. 6,555,759, which employ a compliant photo patternable polymer as the core of an I/O bump so as to provide sufficient compliance to absorb the expansion differential between two electrical devices interconnecting thereby. However, many additional processes are needed in order to fabricate bumps on the integrated circuit (IC) chip by the forgoing method that lead to a decrease in chip production yield and an increase in production cost.
To address the deficiencies of the above processes, presented herein are a novel structures and method of fabrication which are capable of buffering the strain on the interconnection bumps between a first and second electrical devices.